This application claims the benefit of Korean Patent Application No. 2001-6188, filed on Feb. 8, 2001, under 35 U.S.C. xc2xa7119, the entirety of which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a memory system having memory devices for storing data, and more particularly, to an apparatus for providing reference voltages to memory modules on which semiconductor memory devices are mounted.
2. Description of Related Art
FIG. 1 is a schematic view illustrating a configuration of a typical Rambus memory system. The Rambus memory system includes a master element 11 having a Rambus ASIC cell (RAC) and a Rambus memory controller (see 21 FIG. 2A), Rambus in-line module (RIMM) connectors 12 to 14, first and second RIMM memory modules 15 and 16 mounted on the RIMM connectors 12 and 13, a RIMM continuity module 17, and a direct Rambus clock generator (DRCG) 18. The RIMM memory modules 15 and 16 each include a plurality of Rambus DRAMs (RDRAMs), e.g., 256 MB direct RDRAMs.
A Rambus channel 19 provides an interface between the master element 11 and the RDRAMs of each of the first and second RIMM memory modules 15 and 16. The Rambus channel 19 is a transmission line connected between the master element 11 and a terminal resistor Rterm to which a terminal voltage Vterm is applied. The Rambus channel 19 can support a predetermined number of RDRAMs, e.g., 32 RDRAMs, without additional drivers.
In the Rambus memory system of FIG. 1, reference voltages applied to the respective RIMM memory modules 15 and 16 mounted on the respective RIMM connectors 12 and 13 are all equal to each other in level. That is, the reference voltages with the same level are applied to the RDRAMs of the RIMM memory module 15 and the RDRAMs of the RIMM memory module 16.
FIGS. 2A and 2B are block diagrams illustrating a conventional system of providing a reference voltage Vref to RIMM memory modules in a Rambus memory system. As shown in FIGS. 2A and 2B, a memory controller 21 is connected to each of the first and second RIMM memory modules 22 and 23 mounted on the RIMM connectors 12 and 13 (referring to FIG. 1), respectively, through a Rambus channel 24. The reference voltage Vref is applied from a reference voltage source 25 to each of the RIMM memory modules 22 and 23, including RDRAMs 22-1 and 22-2 of the first RIMM memory module 22 and RDRAMs 23-1 and 23-2 of the second RIMM memory module 23.
The reference voltage source 25 includes serial resistors R21 and R22 that are serially connected between the terminal voltage Vterm and ground. The reference voltage source 25 supplies the reference voltage Vref that is voltage-divided by the serial resistors R21 and R22, to the RDRAMs 22-1 and 22-2 of the RIMM memory module 22 and to the RDRAMs 23-1 and 23-2 of the RIMM memory module 23. As a result, the same level reference voltage is applied to the respective RDRAMs 22-1, 22-2, 23-1 and 23-2.
Each of the RDRAMs 22-1 to 23-2 includes a DRAM core region, a Rambus interface, and an analog region for a delay lock loop (DLL) and a power supply. The DRAM core region is almost the same as a typical DRAM core. The Rambus interface is to provide an interface between the DRAM core region and an external portion of a memory chip, and an open drain type driver is widely used as the Rambus interface.
FIG. 3 is a circuit diagram illustrating an example of the open drain type Rambus interface. When an NMOS transistor MN of a driver 31 is turned on, the Rambus interface of FIG. 3 outputs data having a logic xe2x80x9clowxe2x80x9d level. When the NMOS transistor MN is turned off, the Rambus interface of FIG. 3 outputs data having a logic xe2x80x9chighxe2x80x9d level which is obtained from the terminal voltage Vterm connected to the terminal resistor Rterm. In FIG. 3, the reference numeral xe2x80x9c32xe2x80x9d denotes an output terminal.
FIG. 4 shows an example of a Rambus signaling level (RSL) output level of the conventional RDRAM. When the RDRAM normally outputs data of the RSL output level through the Rambus interface of FIG. 3, the level of a high voltage Voh (i.e., the terminal voltage Vterm) that is set to logic xe2x80x9c0xe2x80x9d is about 1.8 volts, the level of the reference voltage Vref is about 1.4 volts, and the level of a low voltage Vol that is set to logic xe2x80x9c1xe2x80x9d is 1.0 volt. Therefore, the normal RSL output level has Vohxe2x88x92Vref=Volxe2x88x92Vref, and has a voltage swing Vsw of about 0.8 volts. The RDRAM can have the RSL output level having an amplitude less than 1.0 volt by terminating one end of the Rambus channel and connecting the terminated end to the terminal voltage Vterm having a level of about 1.8 volts that is lower than a power voltage for a driving current to pass through the terminal resistor Rterm.
However, in the conventional Rambus memory system, when data is read from one of the RDRAMs of one RIMM memory module and data are continuously, without any gap, read from one of the RDRAMs of another RIMM memory module, a so called xe2x80x9cback-to-back noisexe2x80x9d may be generated from the data read from a RDRAM of one RIMM memory module, affecting data read from a RDRAM of another RIMM memory module.
FIG. 5 is a schematic block diagram illustrating a conventional Rambus memory system having three kinds of waves generated due to inherent characteristics of the Rambus channel whose one end is terminated. When data is read from one of the RDRAMs of a RIMM memory module, three types of waves are generally generated such as an incident read wave W1, a reflected wave W2, and an incident terminating wave W3.
The incident read wave W1 proceeds from one of the RDRAMs 42 to 44 to the memory controller 41. The reflected wave W2 is generated due to the reflection of the incident wave W1 from the memory controller 41. The incident terminating wave W3 proceeds from the RDRAMs to the terminal resistor Rterm. The three waves W1 to W3 have a level of Vsw/2 (here, Vsw is the voltage swing shown in FIG. 4).
FIG. 6 is a waveform diagram illustrating the different states of the three waves W1 to W3 of FIG. 5 when data are normally read from the RDRAMs. In FIG. 6, xe2x80x9cT=0xe2x80x9d to xe2x80x9cT=4xe2x80x9d each denotes a lapse of time. As shown in FIG. 6, data can be read normally when there is no back-to-back noise due to a previous read operation. However, when noise (e.g., back-to-back noise) due to a previous read operation occurs, the noise affects the next data read operation as shown in FIG. 7.
FIG. 7 is a waveform diagram illustrating the waves affected by the back-to-back noise. In FIG. 7, references W11 to W13 denote the three types of waves generated when data are read from a RDRAM during a first read cycle, and references W21 to W23 denote the three types of waves generated when data is read from the RDRAM during a second read cycle. As shown in FIG. 7, the reflected wave W12 generated during the first read cycle and the incident terminating wave W23 generated during the second read cycle are overlapped at time T4, so that the RDRAM is driven at a relatively low voltage when data is read from the RDRAM 62. Therefore, a problem exists that data is erroneously read from the RDRAM 62, leading to an abnormal operation.
That is, since the same reference voltage is applied to all of the memory modules, the RSL output level of data outputted from the RDRAM varies. As a result, the relation of Volxe2x88x92Vref=Vrefxe2x88x92Vol (referring to FIG. 4) cannot be maintained and data cannot be read normally. Thus, abnormal operations occur due to the back-to-back noise in the conventional Rambus memory system.
In efforts to overcome the problem described above, there has been proposed a Rambus memory system employing an xe2x80x9cover driving factorxe2x80x9d (ODF) technique in which a driving capability of the system during a data read operation is controlled according to conditions of memory modules of the system. However, the Rambus memory system employing the ODF technique also has problems such as degradation of other driving parameters (e.g., tQmax/Qmin) and a decrease in manufacturing yield.
Therefore, a need exists for a Rambus memory system in which no abnormal read operation occurs due to the back-to-back noise.
Preferred embodiments of the present invention are provided to describe a semiconductor memory device which overcomes the above and other problems in the conventional memory system and has high reliability and manufacturing yield.
In an aspect of the present invention, a memory system includes a plurality of slots for receiving the plurality of memory modules, each memory module having semiconductor memories, wherein each of the plurality of memory modules is applied a different level of reference voltage.
According to another aspect of the present invention, a memory system includes a plurality of memory slots; a plurality of memory modules each having semiconductor memory devices and being mounted on corresponding ones of the memory slots; and a reference voltage source for providing different reference voltages to the memory modules, wherein each reference voltage is provided to memory devices of a corresponding memory module.
In another aspect of the present invention, a memory system includes a plurality of memory slots; a plurality of memory modules each having semiconductor memory devices and being mounted on corresponding one of the memory slots; a reference voltage source for generating an external reference voltage; and a plurality of voltage regulators each being associated with corresponding one of the memory modules, each of the voltage regulators receiving the external reference voltage and regulating the external reference voltage in response to a control signal to provide a reference voltage to corresponding one of the memory modules, wherein the reference voltages having differenct voltage levels are provided to the respective memory modules.
The memory system according to the preferred embodiments of the present invention has the following advantage. Since the reference voltages with different levels are applied to the memory modules, the system is not affected by a noise generated by the previously read data can be reduced and data can be read normally. Thus, high reliability and manufacturing yield can be accomplished.